Recently, to meet the demand for electronic equipment which are both compactly sized and highly functional, a number of technologies for increasing the mounting density of semiconductor devices have been developed. Such technologies include a semiconductor device having a chip-on-chip structure and a semiconductor device having a package-on-package structure.
FIG. 20 of WO 99/56313 shows a semiconductor device in which a plurality of semiconductor packages are stacked by means of a solder ball provided on the tip of a through electrode provided on a lead frame. Published Japanese Translation of PCT Application No. JP-T-2000-510993 discloses a method for mounting electronic equipment on a wiring circuit body by using a clamping piece. Japanese Patent Application Publication No. JP-A-2003-151714 discloses a semiconductor device that electrically couples electronic equipment and wires to each other by using a connector pin.
However, increasing the mounting density of semiconductor devices remains an issue. For example, a semiconductor device having a chip-on-chip structure has a problem that chips are prone to breakage and chips which are stacked are unable to be isolated for repair or disposal, subsequently making it difficult to increase the yield in the mounting process.
Conversely, a semiconductor device having a package-on-package structure has a higher yield compared to the semiconductor device having a chip-on-chip structure, however packages are prone to be thermally deformed due to soldering when stacking, and, unfortunately stably stacking a plurality of semiconductor devices according to conventional techniques can be extremely difficult.
FIG. 1 is a cross-sectional view of a semiconductor device having a chip-on-chip structure according to a conventional example. On an upper surface of an interposer 84, a semiconductor chip 80 having an upper surface on which a circuit is formed is stacked via an adhesive 82. An external electrode (not shown) provided on the upper surface of the semiconductor chip 80 and a coupling terminal (not shown) on the interposer 84 are electrically coupled to each other by a wire 86. On a lower surface of the interposer 84, a solder ball 88 is provided for electrically coupling with the outside. On the upper surface of the interposer 84, a resin section 89 is provided that molds the semiconductor chip 80 and the wire 86. According to such a structure, more than one such semiconductor chip 80 can be provided on one package, thereby potentially increasing the packaging density of the semiconductor devices.
A semiconductor device having the chip-on-chip structure described in FIG. 1 will have a plurality of semiconductor chips mounted on one semiconductor package. Accordingly, in a case where one of the semiconductor chips mounted is defective, non-defective semiconductor chips mounted together also need to be discarded. Therefore, increasing the yield in the mounting process is difficult, and can result in increasing costs. Furthermore, since the semiconductor chips need to be made smaller in order to increase the density, defectives are likely to be produced during manufacturing process.
FIG. 2 is a cross-sectional view of a semiconductor device having a package-on-package structure according to another conventional example. With respect to FIG. 1, identical structures have been assigned corresponding reference numerals and descriptions thereof shall be omitted. A first semiconductor package 90 and a second semiconductor package 92 each include the semiconductor chip 80, the adhesive 82, interposers 84a and 84b, the wire 86, and the resin section 89. A first solder ball 94 provided on a lower surface of the interposer 84a of the first semiconductor package 90 is bonded to an upper surface of the interposer 84b of the second semiconductor package 92. On a lower surface of the interposer 84b of the second semiconductor package 92, a second solder ball 96 for electrically coupling with the outside is provided. By employing such a structure, more than one such semiconductor package can be stacked vertically, whereby the mounting density of the semiconductor devices can be increased.
In a semiconductor device having the package-on-package structure of FIG. 2, a mechanical characteristic test and an electrical characteristic test are performed after packaging the semiconductor chip. Accordingly, only non-defective semiconductor packages are stacked. Further, the semiconductor chips are protected from external shock by the resin section. Accordingly, a semiconductor device having a package-on-package structure has higher yield in mounting process compared to a semiconductor device having a chip-on-chip structure. However, since the first semiconductor package 90 is mechanically and electrically coupled to the second semiconductor package 92 by melting and solidifying the first solder ball 94, the second semiconductor package 92 is deformed by the heat when melting the solder ball 94. Thus, the second semiconductor package 92 cannot be successfully joined to the first semiconductor package 90 in some cases. In the semiconductor device having a package-on-package structure, yield is susceptible to decrease due to thermal deformation as the number of the stacked semiconductor packages increases. Therefore, increasing the mounting density of the semiconductor devices is difficult.